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1999 microchip technology inc. ds21170d-page 1 features ? iso standard 7816 pad locations ? low power cmos technology - 1 ma active current typical - 10 a standby current typical at 5.5v ? organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8) ? 2-wire serial interface bus, i 2 c? compatible ? 100 khz and 400 khz compatibility ? self-timed write cycle (including auto-erase) ? page-write buffer for up to 8 bytes ? 2 ms typical write cycle time for page-write ? esd protection > 4 kv ? 1,000,000 e/w cycles guaranteed ? data retention > 200 years ? available for extended temperature ranges description the microchip technology inc. 24c01sc and 24c02sc are 1k-bit and 2k-bit electrically erasable proms with bondpad positions optimized for smart card applications. the devices are organized as a sin- gle block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. the 24c01sc and 24c02sc also have page-write capability for up to 8 bytes of data. - commercial (c): 0c to +70c die layout block diagram sda dc v cc scl v ss hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic sda scl v cc v ss 1k/2k 5.0v i 2 c ? serial eeproms for smart cards 24c01sc/02sc i 2 c is a trademark of philips corporation.
24c01sc/02sc ds21170d-page 2 1999 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v cc +1.0v storage temperature ..................................... -65c to +150c ambient temp. with power applied ................-65c to +125c esd protection on all pads............................................ ?4 kv *notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pad function table name function v ss sda scl v cc dc ground serial address/data i/o serial clock +4.5v to 5.5v power supply dont connect table 1-2: dc characteristics figure 1-1: bus timing start/stop v cc = +4.5v to +5.5v commercial (c): tamb = 0c to +70c parameter symbol min. max. units conditions scl and sda pads: high level input voltage v ih .7 v cc low level input voltage v il .3 v cc v hysteresis of schmidt trigger inputs v hys .05 v cc v (note) low level output voltage v ol .40vi ol = 3.0 ma, v cc = 4.5v input leakage current (scl) i li -10 10 a v in = .1v to 5.5v output leakage current (sda) i lo -10 10 a v out = .1v to 5.5v pin capacitance (all inputs/outputs) c in , c out 10pfv cc = 5.0v (note 1) tamb = 25c, f clk = 1 mhz operating current i cc write 3 ma v cc = 5.5v i cc read 1 ma vcc = 5.5v, scl = 400 khz standby current i ccs 100 a v cc = 5.5v, sda = scl = v cc note: this parameter is periodically sampled and not 100% tested. scl sda t su : sta t hd : sta start stop v hys t su : sto
1999 microchip technology inc. ds21170d-page 3 24c01sc/02sc table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol min. max. units remarks clock frequency f clk 400 khz clock high time t high 600 ns clock low time t low 1300 ns sda and scl rise time t r 300 ns (note 1) sda and scl fall time t f 300 ns (note 1) start condition hold time t hd : sta 600 ns after this period the first clock pulse is generated start condition setup time t su : sta 600 ns only relevant for repeated start condition data input hold time t hd : dat 0 ns (note 2) data input setup time t su : dat 100 ns stop condition setup time t su : sto 600 ns output valid from clock t aa 900 ns (note 2) bus free time t buf 1300 ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of 20 +0.1 cb 250 ns (note 1), cb e 100 pf input filter spike suppression (sda and scl pins) t sp 50 ns (note 3) write cycle time t wr 10 ms byte or page mode endurance 1m cycles 25c, vcc = 5v, block mode (note 4) note 1: not 100% tested. cb = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific application, please consult the total endurance model which can be obtained on our website. scl sda in sda out t hd : sta t su : sta t f t high t r t su : sto t su : dat t hd : dat t buf t aa t hd : sta t aa t sp t low
24c01sc/02sc ds21170d-page 4 1999 microchip technology inc. 2.0 functional description the 24c01sc/02sc supports a bi-directional two-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and gener- ates the start and stop conditions, while the 24c01sc/02sc works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first in first out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. note: the 24c01sc/02sc does not generate any acknowledge bits if an internal pro- gramming cycle is in progress. figure 3-1: data transfer sequence on the serial bus scl sda ( a ) (b) (d) (d) (c) ( a ) start condition address or acknowledge valid data allowed to change stop condition
1999 microchip technology inc. ds21170d-page 5 24c01sc/02sc 3.6 slave address after generating a start condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24c01sc/02sc, followed by three don't care bits. the eighth bit of slave address determines if the master device wants to read or write to the 24c01sc/02sc (figure 3-2). the 24c01sc/02sc monitors the bus for its corre- sponding slave address all the time. it generates an acknowledge bit if the slave address was true, and it is not in a programming mode. figure 3-2: control byte allocation operation control code chip select r/w read write 1010 1010 xxx xxx 1 0 x = dont care r/w a 1010xxx read/write start slave address 4.0 write operation 4.1 byte write following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the r/w bit, which is a logic low, is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24c01sc/02sc. after receiving another acknowledge signal from the 24c01sc/02sc, the master device will transmit the data word to be written into the addressed memory location. the 24c01sc/02sc acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24c01sc/02sc will not generate acknowledge signals (figure 4-1). 4.2 page write the write control byte, word address, and the first data byte are transmitted to the 24c01sc/02sc in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to eight data bytes to the 24c01sc/02sc, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condi- tion. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains constant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (figure 4-2). note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary.
24c01sc/02sc ds21170d-page 6 1999 microchip technology inc. figure 4-1: byte write figure 4-2: page write s p s t a r t s t o p bus activity master sda line bus activity a c k a c k a c k control byte word address data s p bus activity master sda line bus activity s t a r t s t o p control byte word address (n) data n datan + 7 datan + 1 a c k a c k a c k a c k a c k
1999 microchip technology inc. ds21170d-page 7 24c01sc/02sc 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack, and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes 6.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 6.1 current address read the 24c01sc/02sc contains an address counter that maintains the address of the last word accessed, inter- nally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24c01sc/02sc issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c01sc/02sc discontinues transmission (figure 6-1). 6.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24c01sc/02sc as part of a write operation. after the word address is sent, the master generates a start con- dition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the 24c01sc/02sc will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c01sc/02sc discontinues trans- mission (figure 6-2).
24c01sc/02sc ds21170d-page 8 1999 microchip technology inc. 6.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24c01sc/02sc trans- mits the first data byte, the master issues an acknowledge as opposed to a stop condition in a ran- dom read. this directs the 24c01sc/02sc to transmit the next sequentially addressed 8-bit word (figure 6-3). to provide sequential reads the 24c01sc/02sc con- tains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 6.4 noise protection the 24c01sc/02sc employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 6-1: current address read figure 6-2: random read figure 6-3: sequential read sp bus activity master sda line bus activity s t a r t control byte data n a c k n o a c k s t o p s p s bus activity master sda line bus activity s t a r t s t o p control byte word address (n) data n a c k a c k n o a c k control byte a c k s t a r t p sda line bus activity s t o p control byte data n a c k n o a c k a c k a c k a c k data n + 1 data n + 2 data n + x bus activity master
1999 microchip technology inc. ds21170d-page 9 24c01sc/02sc 7.0 pad descriptions 7.1 sda serial address/data input/output this is a bi-directional pad used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10k? for 100 khz, 2 k? for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 7.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 7.3 dc dont connect this pad is used for test purposes and should not be bonded out. it is pulled down to v ss through an internal resistor. 8.0 die characteristics figure 8-1 shows the die layout of the 24c01sc/02sc, including bondpad positions. table 8-1 shows the actual coordinates of the bondpad midpoints with respect to the center of the die. figure 8-1: die layout table 8-1: bondpad coordinates pad name pad midpoint, x dir. pad midpoint, y dir. v ss -495.000 749.130 sda -605.875 -271.875 scl 479.875 -746.625 v cc 605.875 -261.375 note 1: dimensions are in microns. 2: center of die is at the 0,0 point. dip sda dc v cc scl v ss
24c01sc/02sc ds21170d-page 10 1999 microchip technology inc. notes:
24c01sc/02sc 1999 microchip technology inc. ds21170d-page 11 24c01sc/02sc product identification system to order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system 4. register on our web site (www.microchip.com/cn) to receive the most current information on our products. die thickness blank = 11 mils 08 = 8 mils other die thicknesses available, please consult factory. package: s = die in wafer pak w = wafer wf = sawed wafer on frame temperature blank = 0 c to +70 c range: device: 24c01sc 1k 1 2 c iso smart card die 24c02sc 2k 1 2 c iso smart card die 24c01sc/02sc /s
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